本文件參考自教育部主辦之「八十七學年度大學院校Silicon Intellectual Property創作競賽」， 您亦可自行到下面WEB參考比賽詳情： http://cadal3.cie.nsysu.edu.tw/news/IP_contest_1999/detail.htmSoft IP之不定題組。
Soft IP Deliverables
Required:
Synthesizable Verilog/VHDL codes at behavioral and/or RTL level.
Corresponding synthesis scripts and synthesis constraint files.
Installation guides and scripts.
A reference (synthesized) design targeting to a reference library (CIC provided), and the corresponding area, timing, power, testability reports.
Verification environment and testbench (test patterns) files.
Documentation (suggested items):
Functional description and architecture
Key features and claims
Configuration information and parameters
Comprehensive technical specification and data sheet
Test plan/methods and testability measurement
System-level verification and testing strategy
Application notes, including VHDL/Verilog design examples that instantiate the core.
Optional:
Models for functional verification:
Behavioral models for simulation.
Basic delay models.
Instruction-Set-Architecture (ISA) model for processor/micro-controller designs.
Bus-Functional-Model/Monitors (BFM) for processor/micro-controller designs.
Scripts for scan insertion and ATPG.
Floorplanning shell and constraints.
Others (for IP design automation):
Soft/Hard IP generator
Input: System/module specification.
Output:
Synthesizable VHDL/Verilog codes at behavioral/RTL level for soft IP design.
GDSII file for hard IP design.
Deliverables: A design automation CAD tool, and the outputs meet the Soft/Hard IP deliverables defined in the previous page.
Example: ROM layout generator.
IP design parameter generator
Input: Design constraints for a given IP design.
Output: Design parameters for a given IP design.
Deliverables: A design parameter generator (CAD tool), and the generated parameters can be applied to a given Soft/Hard IP designs.
Example: Design parameter generation for an Over-Sampled Delta-sigma A/D converter circuit.