·
D. D. Gajski, N. Dutt, Allen C.-H. Wu and Steve Y-L Lin, High-Level Synthesis: Introduction to Chip
and System Design, Kluwer Academic Publishers, 1992.
·
C. H. Wu and P. C. Johnson, “A Microcomputer—Based System for Mapping
Microvascular Networks,” Int. Journal
Microcirc: Clin Exp, 8,
p303-311, 1989.
·
Lawrence L. Larmore, D. D. Gajski, and Allen C.-H. Wu, “Layout
Placement for Sliced Architecture,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems,Vol.
11, No. 1, pp. 102-114, January, 1992.
·
Allen C.-H. Wu and D. D. Gajski, “Partitioning Algorithms for
Layout Synthesis from Register-Transfer Netlists,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, Vol. 11, No. 4, pp. 453-463, April, 1992.
·
T. F. Lee, Allen C.-H. Wu, Y. L. Lin and D. D. Gajski, “A
Transformation-Based Method for Loop Folding,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, Vol. 13, No. 4, pp. 439-450, April, 1994.
·
C. D. Chen, Y. S. Lee, Allen C.-H. Wu, and Y. L. Lin,
“TRACER-fpga: A Router for RAM-Based FPGAs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, Vol. 14, No. 3, pp. 371-374, March, 1995.
·
Allen C.-H. Wu and Youn-Long Lin, “High-Level Synthesis-A
Tutorial,” IEICE Transactions Information
& Systems, Vol. E78-D, No. 3, pp. 209-218, March 1995. (Invited Paper: Special Issue on
Synthesis and Verification of Hardware Design)
·
C. S. Chen, Y. W. Tsay, T. T. Hwang, Allen C.-H. Wu, and Y. L.
Lin, “Combining Technology Mapping and Placement for Delay-Minimization in FPGA
Designs,” IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 9,
pp. 1076-1084, September 1995.
·
Tsing-Gen Lee, Wen-Jong Fang, and Allen C.-H. Wu, “The Design
and Implementation of A Cooperative Design-View Environment for Interactive
Partitioning Applications,” Software -
Practice & Experience, Vol. 26(10), pp. 1141-1160, Oct. 1996.
·
Allen C.-H. Wu, “Datapath Optimization Using Layout Information:
An Empirical Study,”, VLSI Design,
Vol. 5, No. 2, pp. 195-209, 1997.
·
Y.-S. Lee and Allen C.-H. Wu, “A Performance and Routability
Driven Router for FPGAs Considering Path Delays,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, Vol. 16, No. 2, pp. 179-185, February 1997.
·
Yann-Rue Lin, Cheng-Tsung Hwang, and Allen C.-H. Wu “Scheduling
Techniques for Variable Voltage Low Power Designs”, ACM Transactions on Design Automation of Electronic Systems, Vol.
2, No. 2, pp. 81-97, April 1997.
·
W.-J. Fang and Allen C.-H. Wu, “A Hierarchical Functional
Structuring and Partitioning Approach for Multiple-FPGA Implementations,” IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems, Vol. 16, No. 10, pp. 1188-1195,
October, 1997.
·
W.-J. Fang and Allen C.-H. Wu, “Exploiting the Interaction
between HDL Synthesis and Partitioning for High Density Multi-FPGA Designs,” IEEE Design & Test of Computers,
pp.65-72, Vol. 5, No. 2, April-June, 1998.
·
H.-P. Su, Allen C.-H. Wu, and Y.-L. Lin, “A Timing-Driven
Soft-Macro Placement and Resynthesis Method in Interaction with Chip
Floorplanning”, IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, pp. 475-483, Vol.
18, No. 4, April 1999.
·
W.-J. Fang, Allen C.-H. Wu, and D.-P. Chen, “EmGen: A Module
Generator for Logic-Emulation Applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
pp. 488-492, Vol. 7, No. 4, December 1999.
·
W.-J. Fang and Allen C.-H. Wu, “Multi-Way FPGA Partitioning by
Fully Exploiting Design Hierarchy,” ACM
Transactions on Design Automation of Electronic Systems, pp. 34-50, Vol.
15, No. 1, January 2000 .
·
C.-H. Hwang and Allen C.-H. Wu, “A Predictive System Shutdown
Method for Energy Saving of Event-Driven Computation,” ACM Transactions on Design Automation of Electronic Systems, pp.
226-241, Vol. 5, No. 2, April 2000.
·
N. Vander Zanden, Allen C.-H. Wu, and D. D. Gajski, “Technology
Mapping with Layout Constraints,” International
Symposium on VLSI Technology, Systems and Applications, Taipei, Taiwan, pp.
227-231, May, 1989.
·
Allen C.-H. Wu, N. Vander Zanden, and D. D. Gajski, “An Algorithm
for Transistor Sizing in CMOS Circuits,” The
European Conference on Design Automation (EDAC), Glasgow, Scotland, pp.
589-593, March, 1990.
·
Allen C.-H. Wu, G. D. Chen, and D. D. Gajski, “Silicon Compilation
from Register-Transfer Schematics,” International
Symposium Circuits and Systems (ISCAS), pp. 2576-2579, 1990.
·
Allen C.-H. Wu and D. D. Gajski, “Partitioning Algorithms
forLayout Synthesis from Register-Transfer Netlists,” International Conference on Computer-Aided Design (ICCAD), Santa
Clara, CA, pp. 144-147, November, 1990.
·
Allen C.-H. Wu and D. D. Gajski, “Glue-Logic Partitioning for
Floorplans with A Rectilinear Datapath,” The
European Conference on Design Automation (EDAC), Amsterdam, Netherlands,
pp. 162-166, February, 1991.
·
N. Vander Zanden, Allen C.-H. Wu, and D. D. Gajski, “Logic
Synthesis for Custom Layout,” The
European Conference on Design Automation (EDAC), Amsterdam, Netherlands,
pp. 588, February, 1991.
·
Allen C.-H. Wu, G. D. Chen and D. D. Gajski, “Evaluation Driven
Layout Synthesis,” International
Symposium on VLSI Technology, Systems and Applications, Taipei, Taiwan, pp.
167-171, May, 1991.
·
Allen C.-H. Wu, V. Chaiyakul, and D. D. Gajski, “Layout Models for
High-Level Synthesis,” International
Conference on Computer-Aided Design (ICCAD), Santa Clara, CA, pp.34-37,
November, 1991.
·
D. D. Gajski, Allen C.-H. Wu, and Viraphol Chaiyakul, “Layout
Synthesis and Layout Models for Synthesis,” Synthesis
and Simulation Meeting and International Interchange (SASIMI), Kobe, Japan,
pp. 393-405, 1992.
·
T. F. Lee, Allen C.-H. Wu and Steve Y. L. Lin, “A New Algorithm
for Pipelining Loop Execution,” Synthesis
and Simulation Meeting and International Interchange (SASIMI), Kobe, Japan,
pp. 198-207, 1992.
·
Viraphol Chaiyakul, Allen C.-H. Wu and D. D. Gajski, “Timing
Models for High Level Synthesis,” EURO-DAC’92,
Hamburg, Germany, pp. 60-65, September, 1992.
·
Allen C.-H. Wu, Tedd S. Hadley and D. D. Gajski, “An Efficient
Multi-View Design Model for Real-Time Interactive Synthesis,” International Conference on Computer-Aided
Design (ICCAD), Santa Clara, CA, pp. 328-331, November, 1992.
·
C. Ramachandran, F. J. Kurdahi, D. D. Gajski, Allen C.-H. Wu and
V. Chaiyakul, “Accurate Layout Area and Delay Modeling for System Level
Design,” International Conference on
Computer-Aided Design (ICCAD), Santa Clara, CA, pp. 355-361, November,
1992.
·
T. F. Lee, Allen C.-H. Wu, D. D. Gajski and Y. L. Lin, “An
Effective Methodology for Functional Pipelining,” International Conference on Computer-Aided Design (ICCAD), Santa
Clara, CA, pp. 230-233, November, 1992.
·
Y. W. Tsay, Allen C.-H. Wu, and Y. L. Lin, “A Cell Placement
Procedure That Utilizes Circuit Structural Properties,” The European Conference on Design Automation (EDAC-EUROASIC),
Paris, France, pp. 189-193, February, 1993.
·
C. S. Chen, Y. W. Tsay, T. T. Hwang, Allen C.-H. Wu, and Y. L.
Lin, “Combining Technology Mapping and Placement for Standard Cell Based
Designs,” Synthesis and Simulation
Meeting and International Interchange (SASIMI), Japan, 394-403, 1993.
·
W. J. Chen, W. K. Cheng, T. F. Lee, Allen C.-H. Wu, and Y. L.
Lin, “On the Relationship Between Sequential Logic Retiming and Loop Folding,” Synthesis and Simulation Meeting and
International Interchange (SASIMI), Japan, pp. 384-393, 1993.
·
C. S. Chen, Y. W. Tsay, T. T. Hwang, Allen C.-H. Wu, and Y. L.
Lin, “Combining Technology Mapping and Placement for Delay-Minimization in FPGA
Designs,” International Conference on
Computer-Aided Design (ICCAD), San Jose, CA, pp. 123-127, 1993.
·
T.-Y. Wu, T.-Z. Tien, Allen C.-H. Wu, and Y. L. Lin, “A
Synthesis Method for Mixed Synchronous/Asynchronous Behavior,” The European Conference on Design Automation
(EDAC-ETC-EUROASIC), Paris, France, pp. 277-281, February, 1994.
·
K.-H. Wang, W.-S. Wang, T. T. Hwang, Allen C.-H. Wu, and Y. L.
Lin,“State Assignment for Power and Area Minimization”, International Conference on Computer Design (ICCD), Cambridge,
Massachusetts, pp. 250-254, 1994.
·
Y.-S. Lee and Allen C.-H. Wu, “A Performance and Routability
Driven Router for FPGAs Considering Path Delays,” The 32rd Design Automation Conference (DAC), San Francisco, CA, pp.
557-561, 1995.
·
T.-G. Lee, W.-J. Fang, and Allen C.-H. Wu, “EMPAR: An
Interactive Synthesis Environment for Hardware Emulations,” Asia and South Pacific Design Automation
Conference (ASP-DAC), Chiba, Japan, pp. 87-92, 1995.
·
W.-J. Fang and Allen C.-H. Wu, “A Hierarchical Functional
Structuring and Partitioning Approach for Multiple-FPGA Implementations,” International Conference on Computer-Aided
Design (ICCAD), San Jose, CA, pp. 638-643, 1996.
·
W.-J. Fang, Allen C.-H. Wu, T.-Y. Yen, and T.-C. Lin “DP_Gen: A
Datapath Generator for Multiple-FPGA Applications,” Asia and South Pacific Design Automation Conference (ASP-DAC),
Chiba, Japan, pp. 563-568, 1997.
·
W.-L. Ing, C.-T. Hwang, and Allen C.-H. Wu, “Evaluating
Cost-Performance Tradeoffs for System Level Applications,” Asia and South Pacific Design Automation Conference (ASP-DAC),
Chiba, Japan, pp. 233-238, 1997.
·
C.-H. Hwang and Allen C.-H. Wu, “An Entropy Measure for Power
Estimation of Boolean Functions,” Asia
and South Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, pp.
101-106, 1997.
·
W.-J. Fang, Allen C.-H. Wu, and D.-P. Chen, “Module Generation
of Complex Macros for Logic-Emulation Applications,” ACM/SIGDA Fifth International Symposium on Field-Programmable Gate
Arrays (FPGA’97), Monterey, CA, pp. 69-75, 1997.
·
Y.-W. Tsay, W.-J. Fang, Allen C.-H. Wu, and Y.-L. Lin,
“Preserving HDL Synthesis Hierarchy for Cell Placement,” International Symposium on Physical Design (ISPD), Napa Valley, CA,
pp. 169-174, 1997.
·
W.-J. Fang, Allen C.-H. Wu, and T.-Y. Yen, “A Real-Time RTL
Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation
Applications,” The 34th Design
Automation Conference (DAC), Anaheim, CA, pp.101-106, 1997.
·
W.-J. Fang and Allen C.-H. Wu, “Multi-Way FPGA Partitioning by
Fully Exploiting Design Hierarchy,” The
34th Design Automation Conference (DAC), Anaheim, CA,
pp.518-521, 1997.
·
W.-J. Fang and Allen C.-H. Wu, “Application-Driven HDL Synthesis
Methodologies for High Density Multi-FPGA Designs,” Asia-Pacific Conference on Hardware Description Languages (APCHDL’97), Hsinchu, Taiwan,
pp.100-106, 1997.
·
C.-H. Hwang and Allen C.-H. Wu, “A Predictive System Shutdown
Method for Energy Saving of Event-Driven Computation,” International Conference on Computer-Aided Design (ICCAD), San
Jose, CA, pp.28-32, 1997.
·
H.-P. Su, Allen C.-H. Wu, and Y.-L. Lin, “Performance-Driven
Soft-Macro Clustering and Placement by Preserving HDL Design Hierarchy,” International Symposium on Physical Design
(ISPD), Monterey, CA, 1998.
·
W.-J. Fang and Allen C.-H. Wu, “Performance-Driven Multi-FPGA
Partitioning Using Functional Clustering and Replication,” The 35th Design Automation Conference (DAC), San
Francisco, CA, 1998.
·
W.-J. Fang, P.-C. Kao, and Allen C.-H. Wu, “A Multi-Level FPGA
Synthesis Method Supporting HDL Debugging for Emulation-Based Designs,” Asia and South Pacific Design Automation
Conference (ASP-DAC), Hong Kong, pp. 351-354, 1999.
·
H.-P. Su, Allen C.-H. Wu, and Y.-L. Lin, “A Timing-Driven
Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning,” The 36th Design Automation
Conference (DAC), New Orleans, LA, pp. 262-267, 1999.
·
D. D. Gajski, A. C.-H. Wu, V. Chaiyakul, S. Mori, T. Nukiyama, and P.
Bricaud, “Essential Issues For IP Reuse”, Asia
and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan,
pp. 37-42, 2000. (Invited Tutorial)
·
Allen C.-H. Wu, B. McNamara, and J. I. Hillawi, “A Methodology for
Automating Design Reuse”, The
International HDL Conference (HDLCON2000), San Jose, CA, pp. 73-79, 2000.
·
Chien-Chu Kuo and Allen C.-H. Wu, “Delay-Budgeting for A
Timing-Closure-Driven Design Method”, International
Conference on Computer-Aided Design (ICCAD), San Jose, CA, 2000.