Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constraint. Seong-Ook Jung, Ki-Wook Kim
and Sung-Mo (Steve) Kang

Power Minimization using Simultaneous Gate Sizing, Dual-Vdd and Dual-Vth Assignment. Ashish Srivastava Dennis Sylvester David Blaauw

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, Conrad Ziesler, David Blaauw, Todd Austin, Krisztian Flautner, and Trevor Mudge

Exploiting Crosstalk to Speed up On-chip Buses. Chunjie Duan and Sunil P. Khatri

Re-configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-micron Instruction Bus. Siu-Kei Wong, Chi-Ying Tsui

Bus Encoding to Prevent Crosstalk Delay. Bret Victor and Kurt Keutzer

Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion. Pietro Babighian, Luca Benini, Alberto Macii, and  Enrico Macii

Lowering power consumption in clock by using Globally Asynchronous Locally synchronous design style. A. Hemani, T. Meincke, S. Kumar, A. Postula, T. Olsson, P. Nilsson, J. Oberg, P. Eliervee, and D. Lundqvist

A New Heuristic Algorithm for Reversible Logic Synthesis. Pawel Kerntopf