Publications

 
Publications

Books & Book Chapters (1)
[1]

Journal Papers (12)
[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]

Conference Papers (54)
[14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] [59] [60] [61] [62] [63] [64] [65] [66] [67]

Patents (11)
[68] [69] [70] [71] [72] [73] [74] [75] [76] [77] [78]

Other Publications (5)
[79] [80] [81] [82] [83]

A. BOOKS & BOOK CHAPTERS

1
C.-W. Wu and C.-T. Huang,
SOC Testing and Design for Testability,
in Essential Issues in SOC Design: Designing Complex Systems-on-Chip. Ed. Y.-L. Lin, Springer, 2006.

B. JOURNAL PAPERS

2
C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang,
``A programmable BIST core for embedded DRAM'',
IEEE Design & Test of Computers, vol. 16, no. 1, pp. 59-70, Jan.-Mar. 1999.
3
C.-T. Huang and C.-W. Wu,
``High-speed easily testable Galois-field inverter'',
IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 9, pp. 909-918, Sept. 2000.
4
C.-W. Wu, J.-F. Li, and C.-T. Huang,
``Core-based system-on-chip testing: Challenges and opportunities'',
J. Chinese Institute of Electrical Engineering, vol. 8, no. 4, pp. 335-353, Nov. 2001.
5
C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu,
``Fault simulation and test algorithm generation for random access memories'',
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 4, pp. 480-490, Apr. 2002.
6
C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu,
``Built-in redundancy analysis for memory yield improvement'',
IEEE Trans. Reliability, vol. 52, no. 4, pp. 386-399, Dec. 2003.
7
C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu,
``A high-throughput low-cost AES processor'',
IEEE Communications Magazine, vol. 41, no. 12, pp. 86-91, Dec. 2003.
8
Y.-L. Peng, C.-W. Wu, J.-J. Liou, and C.-T. Huang,
``BIST-based diagnosis scheme for FPGA interconnect delay faults'',
IET Computers & Digital Techniques, vol. 1, no. 6, pp. 716-723, Nov. 2007.
9
C.-H. Lin, C.-T. Huang, C.-P. Jiang, and S.-C. Chang,
``Optimization of pattern matching circuits for regular expression on FPGA'',
IEEE Trans. VLSI Systems, vol. 15, no. 12, pp. 1303-1310, Dec. 2007.
10
J.-Y. Lai and C.-T. Huang,
``Elixir: High-throughput cost-effective dual-field processors and the design framework for elliptic curve cryptography'',
IEEE Trans. VLSI Systems, vol. 16, no. 11, pp. 1567-1580, Nov. 2008.
11
J.-Y. Lai and C.-T. Huang,
``A highly efficient cipher processor for dual-field elliptic curve cryptography'',
IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 56, no. 5, pp. 394-398, May 2009.
12
M.-Y. Wang, C.-P. Su, C.-L. Horng, C.-W. Wu, and C.-T. Huang,
``Single- and multi-core configurable AES architectures for flexible security'',
IEEE Trans. VLSI Systems, vol. 18, no. 4, pp. 541-552, Apr. 2010.
13
J.-Y. Lai and C.-T. Huang,
``Energy-adaptive dual-field processors for high-performance elliptic curve cryptographic applications'',
IEEE Trans. VLSI Systems, Apr. 2010 (in press).

C. CONFERENCE PAPERS

14
C.-T. Huang and C.-W. Wu,
``High-speed C-testable bit-level systolic arrays for GF(2m) inversion'',
in Proc. Sixth VLSI Design/CAD Symp., Chiayi, Aug. 1995, pp. 136-139.
15
C.-T. Huang and C.-W. Wu,
``VLSI design of a high speed pipelined Reed-Solomon CODEC'',
in Proc. Int. Symp. Multi-Technology Inform. Processing (ISMIP), Hsinchu, Dec. 1996, pp. 517-522.
16
C.-T. Huang and C.-W. Wu,
``High-speed C-testable systolic array design for Galois-field inversion'',
in Proc. European Design and Test Conf. (ED&TC), Paris, Mar. 1997, pp. 342-346.
17
C.-P. Su, C.-T. Huang, and C.-W. Wu,
``DFT methodologies for a communications processor core'',
in Proc. 9th VLSI Design/CAD Symp., Nantou, Aug. 1998, pp. 161-164.
18
C.-F. Wu, C.-T. Huang, and C.-W. Wu,
``RAMSES: a fast memory fault simulator'',
in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Albuquerque, Nov. 1999, pp. 165-173.
19
C.-T. Huang, J.-R. Huang, and C.-W. Wu,
``A programmable built-in self-test core for embedded memories'',
in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2000, pp. 11-12,
(Design contest).
20
C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu,
``Simulation-based test algorithm generation for random access memories'',
in Proc. IEEE VLSI Test Symp. (VTS), Montreal, Apr. 2000, pp. 291-296.
21
C. Cheng, C.-T. Huang, J.-R. Huang, C.-W. Wu, C.-J. Wey, and M.-C. Tsai,
``BRAINS: A BIST complier for embedded memories'',
in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Yamanashi, Oct. 2000, pp. 299-307.
22
C.-F. Wu, C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W. Wu,
``Error catch and analysis for semiconductor memories using March tests'',
in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), San Jose, Nov. 2000, pp. 468-471.
23
C.-F. Wu, C.-T. Huang, K.-L. Cheng, C.-W. Wang, and C.-W. Wu,
``Simulation-based test algorithm generation and port scheduling for multi-port memories'',
in Proc. IEEE/ACM Design Automation Conf. (DAC), Las Vegas, June 2001, pp. 301-306.
24
J.-F Li, K.-L. Cheng, C.-T. Huang, and C.-W. Wu,
``March-based RAM diagnosis algorithms for stuck-at and coupling faults'',
in Proc. Int. Test Conf. (ITC), Baltmore, Oct. 2001, pp. 758-767.
25
C.-W. Wang, R.-S. Tzeng, C.-F. Wu, C.-T. Huang, C.-W. Wu, S.-Y. Huang, S.-H. Lin, and H.-P. Wang,
``A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters'',
in Proc. Tenth IEEE Asian Test Symp. (ATS), Kyoto, Nov. 2001, pp. 103-108.
26
K.-L. Cheng, C.-M. Hsueh, J.-R. Huang, J.-C. Yeh, C.-T. Huang, and C.-W. Wu,
``Automatic generation of memory built-in self-test cores for system-on-chip'',
in Proc. Tenth IEEE Asian Test Symp. (ATS), Kyoto, Nov. 2001, pp. 91-96.
27
J.-C. Yeh, C.-F. Wu, K.-L. Cheng, Y.-F. Chou, C.-T. Huang, and C.-W. Wu,
``Flash memory built-in self-test using march-like algorithms'',
in Proc. IEEE Int. Workshop on Electronic Design, Test, and Applications (DELTA), Christchurch, Jan. 2002, pp. 137-141.
28
K.-L. Cheng, J.-C. Yeh, C.-W. Wang, C.-T. Huang, and C.-W. Wu,
``RAMSES-FT: A fault simulator for flash memory testing and diagnostics'',
in Proc. IEEE VLSI Test Symp. (VTS), Monterey, California, Apr. 2002, pp. 281-286.
29
C.-W. Wang, J.-R. Huang, K.-L. Cheng, H.-S. Hsu, C.-T. Huang, C.-W. Wu, and Y.-L. Lin,
``A test access control and test integration system for system-on-chip'',
in Sixth IEEE Int. Workshop on Testing Embedded Core-Based System-Chips (TECS), Monterey, California, May 2002, pp. P2.1-P2.8.
30
T.-F. Lin, C.-P. Su, C.-T. Huang, and C.-W. Wu,
``A high-throughput low-cost AES cipher chip'',
in Proc. 3rd IEEE Asia-Pacific Conf. ASIC, Taipei, Aug. 2002, pp. 85-88.
31
M.-C. Lee, J.-R. Huang, C.-P. Su, T.-Y. Chang, C.-T. Huang, and C.-W. Wu,
``A true random generator desing'',
in Proc. 13th VLSI Design/CAD Symp., Taitung, Aug. 2002, pp. 137-140.
32
Y.-C. Tsai, S.-Y. Huang, C.-P. Su, C.-T. Huang, and C.-W. Wu,
``Fine-grain mixed-level power estimation based on disparity path analysis'',
in Proc. 13th VLSI Design/CAD Symp., Taitung, Aug. 2002, pp. 199-202.
33
Y.-T. Lin, C.-P. Su, C.-T. Huang, C.-W. Wu, S.-Y. Huang, and T.-Y. Chang,
``Low-power embedded memory architecture design for SOC'',
in Proc. 13th VLSI Design/CAD Symp., Taitung, Aug. 2002, pp. 306-309.
34
S.-K. Chiu, J.-C. Yeh, C.-T. Huang, and C.-W. Wu,
``Diagonal test and diagnostic schemes for flash memories'',
in Proc. Int. Test Conf. (ITC), Baltmore, Oct. 2002, pp. 37-46.
35
C.-W. Wang, J.-R. Huang, Y.-F. Lin, K.-L. Cheng, C.-T. Huang, C.-W. Wu, and Y.-L. Lin,
``Test scheduling of BISTed memory cores for SOC'',
in Proc. 11th IEEE Asian Test Symp. (ATS), Guam, Nov. 2002, pp. 356-361.
36
H.-S. Hsu, J.-R. Huang, K.-L. Cheng, C.-W. Wang, C.-T. Huang, C.-W. Wu, and Y.-L. Lin,
``Test scheduling and test access architecture optimization for system-on-chips'',
in Proc. 11th IEEE Asian Test Symp. (ATS), Guam, Nov. 2002, pp. 411-416.
37
M.-C. Sun, C.-P. Su, C.-T. Huang, and C.-W. Wu,
``Design of a scalable RSA and ECC crypto-processor'',
in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Kitakyushu, Jan. 2003, pp. 495-498,
(Best Paper Award).
38
C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu,
``A highly efficient AES cipher chip'',
in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Kitakyushu, Jan. 2003, pp. 561-562,
(Design Contest Special Feature Award).
39
C.-W. Wang, K.-L. Cheng, C.-T. Huang, and C.-W. Wu,
``Test and diagnosis of word-oriented multiport memories'',
in Proc. IEEE VLSI Test Symp. (VTS), Napa Valley, Apr. 2003, pp. 248-253.
40
C.-W. Wang, K.-L. Cheng, J.-N. Lee, Y.-F. Chou, C.-T. Huang, C.-W. Wu, F. Huang, and H.-T. Yang,
``Fault pattern oriented defect diagnosis for memories'',
in Proc. Int. Test Conf. (ITC), Charlotte, Sept. 2003, pp. 29-38.
41
K.-L. Cheng, C.-W. Wang, J.-N. Lee, Y.-F. Chou, C.-T. Huang, and C.-W. Wu,
``FAME: a fault-pattern based memory failure analysis framework'',
in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), San Jose, Nov. 2003, pp. 595-598.
42
M.-Y. Wang, C.-P. Su, C.-T. Huang, and C.-W. Wu,
``An HMAC processor with integrated SHA-1 and MD5 algorithms'',
in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2004, pp. 456-458.
43
C.-H. Wang, C.-P. Su, C.-T. Huang, and C.-W. Wu,
``A word-based RSA crypto-processor with enhanced pipeline performance'',
in Proc. 4th IEEE Asia-Pacific Conf. Advanced System Integrated Circuits (AP-ASIC), Fukuoka, Aug. 2004, pp. 218-221.
44
Y.-T. Hsing, C.-W. Wang, C.-W. Wu, C.-T. Huang, and C.-W. Wu,
``Failure factor based yield enhancement for SRAM designs'',
in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Cannes, Oct. 2004, pp. 20-28.
45
Y.-L. Peng, J.-J. Liou, C.-T. Huang, and C.-W. Wu,
``An application-independent delay testing methodology for island-style FPGA'',
in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Cannes, Oct. 2004, pp. 478-486.
46
K.-L. Cheng, J.-R. Huang, C.-W. Wang, C.-Y. Lo, L.-M. Denq, C.-T. Huang, C.-W. Wu, S.-W. Hung, and J.-Y. Lee,
``An SOC test integration platform and its industrial realization'',
in Proc. Int. Test Conf. (ITC), Charlotte, Oct. 2004.
47
C.-T. Huang, J.-C. Yeh, Y.-Y. Shih, R.-F. Huang, and C.-W. Wu,
``On test and diagnostics of flash memories'',
in Proc. 13th IEEE Asian Test Symp. (ATS), Kenting, Taiwan, Nov. 2004, pp. 260-265.
48
C.-P. Su, C.-L. Horng, C.-T. Huang, and C.-W. Wu,
``A configurable AES processor for enhanced security'',
in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Shanghai, Jan. 2005.
49
C.-P. Su, C.-H. Wang, K.-L. Cheng, C.-T. Huang, and C.-W. Wu,
``Design and test of a scalable security processor'',
in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Shanghai, Jan. 2005.
50
H.-C. Liao, J.-J. Liou, Y.-L. Peng, C.-T. Huang, and C.-W. Wu,
``Delay defect coverage for FPGA test configurations based on statistical evaluation'',
in Proc. Int. Symp. VLSI Technology, Systems, and Applications: Design, Automation and Test (VLSI-TSA-DAT), Hsinchu, Apr. 2005, pp. 217-220.
51
C.-C. Wang, J.-J. Liou, Y.-L. Peng, C.-T. Huang, and C.-W. Wu,
``A BIST scheme for FPGA interconnect delay faults'',
in Proc. IEEE VLSI Test Symp. (VTS), Palm Springs, May 2005, pp. 201-206.
52
J.-C. Yeh, S.-F. Kuo, C.-W. Wu, C.-T. Huang, and C.-H. Chen,
``A systematic approach to reducing semiconductor memory test time in mass production'',
in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Taipei, Aug. 2005, pp. 97-102.
53
C.-H. Wang, J.-C. Yeh, C.-T. Huang, and C.-W. Wu,
``Scalable security processor design and its implementation'',
in Proc. IEEE Asian Solid-State Circuit Conf. (A-SSCC), Hsinchu, Nov. 2005, pp. 513-516.
54
C.-W. Wu, C.-T. Huang, S.-Y. Huang, P.-C. Huang, T.-Y. Chang, and Y.-T. Hsing,
``The HOY tester--Can IC testing go wireless?'',
in Proc. Int'l Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2006, pp. 183-186.
55
C.-H. Lin, C.-T. Huang, C.-P. Jiang, and S.-C. Chang,
``Optimization of regular expression pattern matching circuits on FPGA'',
in Proc. Design, Automation and Test in Europe (DATE), Munich, Mar. 2006, pp. 12-17.
56
C.-H. Wang, C.-Y. Lo, M.-S. Lee, J.-C. Yeh, C.-T. Huang, C.-W. Wu, and S.-Y. Huang,
``A network security processor design based on an integrated SOC design and test platform'',
in Proc. IEEE/ACM Design Automation Conf. (DAC), San Francisco, July 2006.
57
T.-W. Ko, Y.-T. Hsing, C.-W. Wu, and C.-T. Huang,
``Stable performance MAC protocol for HOY wireless tester under large population'',
in Proc. Int'l Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2007, pp. 160-163.
58
S.-Y Lin and C.-T. Huang,
``A high-throughput low-power aes cipher for network applications'',
in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2007, pp. 595-600.
59
J.-J Liou, C.-T. Huang, C.-W. Wu, C.-C. Tien, C.-H. Wang, H.-P. Ma, Y.-Y. Chen, Y.-C. Hsu, L.-M. Deng, C.-J. Chiu, Y.-W. Li, and C.-M. Chang,
``A prototype of a wireless-based test system'',
in Proc. IEEE Int. SOC Conf. (SOCC), Hsinchu, Sept. 2007, pp. 225-228.
60
M.-C. Hsieh and C.-T. Huang,
``An embedded infrastructure of debug and trace interface for the DSP platform'',
in Proc. IEEE/ACM Design Automation Conf. (DAC), Anaheim, June 2008, pp. 866-871.
61
C.-K. Hsu, L.-M. Denq, M.-Y. Wang, J.-J. Liou, C.-T. Huang, and C.-W. Wu,
``Area and test cost reduction for on-chip wireless test channels with system-level design techniques'',
in Proc. 17th IEEE Asian Test Symp. (ATS), Sapporo, Nov. 2008, pp. 245-250.
62
C.-W. Tzeng, C.-Y. Lin, S.-Y. Huang, C.-T. Huang, J.-J. Liou, H.-P. Ma, P.-C. Huang, and C.-W. Wu,
``iScan: Indirect-access scan test over HOY test platform'',
in Proc. Int'l Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2009, pp. 60-63.
63
J.-Y. Lai, T.-Y. Hung, K.-H. Yang, and C.-T. Huang,
``High-performance architecture for elliptic curve cryptography over binary field'',
in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Paris, Aug. 2010, pp. 3933-3936.
64
T.-Y. Li, S.-Y. Huang, H.-J. Hsu, C.-W. Tzeng, C.-T. Huang, J.-J. Liou, H.-P. Ma, P.-C. Huang, J.-C. Bor, C.-W. Wu, C.-C. Tien, and M. Wang,
``AF-Test: Adaptive-frequency scan test methodology for small-delay defects'',
in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Kyoto, Nov. 2010, pp. 340-348.
65
S.-H. Chen, H.-M. Lin, C.-C. Hsieh, C.-T. Huang, J.-J. Liou, and Y.-C. Chung,
``TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler'',
in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2011, pp. 97-98,
(Design contest).
66
S-L. Chen, B.-R. Ke, J.-N. Chen, and C.-T. Huang,
``Reliability analysis and improvement for multi-level non-volatile memories with soft information'',
in Proc. IEEE/ACM Design Automation Conf. (DAC), San Diego, 2011,
(accepted).
67
C.-F. Li, C.-Y. Lee, C.-H. Wang, S.-L. Chang, Y.-S. Kuo, L.-M. Denq, C.-C. Chi, T.-Y. Chang, H.-J. Hsu, M.-Y. Chu, C.-T. Huang, J.-J. Liou, S.-Y. Huang, P.-C. Huang, H.-P. Ma, J.-C. Bor, C.-C. Tien, C.-H. Wang, and C.-W. Wu,
``A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing'',
in Proc. IEEE/ACM Design Automation Conf. (DAC), San Diego, 2011,
(accepted).

D. PATENTS

68
J.-R. Huang, C.-T. Huang, C.-F. Wu, and C.-W. Wu,
``Programmable built in self test for embedded DRAM'',
U.S. Patent No. 6415403, July 2002.
69
S.-K. Chiu, J.-C. Yeh, K.-L. Cheng, C.-T. Huang, and C.-W. Wu,
``Diagonal test schemes for flash memories'',
R.O.C. Patent No. 192282, Dec. 2003,
(in Chinese).
70
C.-W. Wu, J.-R. Huang, C.-F. Wu, and C.-T. Huang,
``Built-in self-test circuit for embedded memory'',
R.O.C. Patent No. 200758, Apr. 2004,
(in Chinese).
71
C. Cheng, C.-T. Huang, J.-R. Huang, and C.-W. Wu,
``Test pattern generator for SRAM and DRAM'',
U.S. Patent No. 6934900, Aug. 2005.
72
C.-W. Wu, C.-T. Huang, C.-W. Wang, and K.-L. Cheng,
``Multi-port memory testing method and computer readable recording media'',
R.O.C. Patent No. I252974, Apr. 2006,
(in Chinese).
73
C.-W. Wu, C.-T. Huang, C.-W. Wang, and K.-L. Cheng,
``Multi-port memory testing method utilizing a sequence folding scheme for testing time reduction'',
U.S. Patent No. 7117409, Oct. 2006.
74
C.-W. Wu, C.-T. Huang, and Y.-T. Hsing,
``Probing system for integrated circuit devices'',
R.O.C. Patent No. I264551, Oct. 2006.
75
S.-K. Chiu, J.-C. Yeh, K.-L. Cheng, C.-T. Huang, and C.-W. Wu,
``Diagonal testing method for flash memories'',
U.S. Patent No. 7065689, June 2006.
76
C.-W. Wu, C.-T. Huang, and Y.-T. Hsing,
``Probing system for integrated circuit device'',
U.S. Patent No. 7675309, Feb. 2010.
77
C.-T. Huang, Y.-J. Ho, and M.-C. Hsieh,
``Trace compression method for debug and trace interface wherein differences of register contents between logically adjacent registers are packed and increases of program counter addresses are categorized'',
U.S. Patent No. 7861070, Dec. 2010.
78
C.-W. Wu, C.-T. Huang, and Y.-T. Hsing,
``Probing system for integrated circuit devices'',
U.S. Patent No. 7904768 B2, Mar. 2011.

E. OTHER PUBLICATIONS

79
C.-T. Huang and C.-W. Wu,
``Overview of memory testing technology'',
IC Design Magazine, vol. 9, pp. 72-76, Dec. 2000,
(in Chinese).
80
C.-W. Wu and C.-T. Huang,
``VLSI Test Technology Forum'',
IC Design Magazine, vol. 12, pp. 86-88, Mar. 2001,
(in Chinese).
81
C.-W. Wu and C.-T. Huang,
``Communications IP: Instruction set architecture, functional units, and test circuitry of a communications processor core'',
NSC Engineering Science & Technology Bulletin, , no. 58, pp. 139-143, Oct. 2001,
(in Chinese).
82
C.-W. Wu, C.-T. Huang, and C.-Y. Wu,
``2001 International Workshop on IC-SOC'',
IEEE Circuits and Systems Magazine, vol. 1, no. 4, pp. 45-46, 4th Quarter 2001.
83
J.-R. Huang and C.-T. Huang,
Verilog HDL--A Guide to Digital Design and Synthesis,
Chuan Hwa Science & Technology Book, Taipei, second edition, 2005,
(Chinese translation of the book with the same title by Samir Palnitkar, Prenitice Hall, 2nd Ed, 0-13-044911-3, 2003.).


Chih-Tsun Huang 2011-04-28

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