Technology Mapping for Domino Logic. Min Zhao and Sachin S. Sapatneker

Compression and Technology Mapping of Logic Circuit. Vinícius Pazzuti Correia and André Inácio Reis

Logic Optimization by Output Phase Assignment in Dynamic Logic Synthesis. Puchir Puri, Andrew Bjorksten and Thomas E. Rosser

The Design of an Asynchronous VHDL Synthesizer. Sun-Yen Tan, Stephen B. Furber and Wen-Fang Yen

洪仲昀

A Transformation Based Algorithm for Reversible Logic Synthesis. D. Michael Miller, Dmitri Maslov, and Gerhard W. Dueck

An ASIC Design Methodology with Predictably Low Leakage, using Leakage-immune Standard Cells. Nikhil Jayakumar and Sunil P Khatri

An MTCMOS Design Methodology and Its Application to Mobile Computing. Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-Myung Choi, and Jeong-Taek Kong

A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown

Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization. Dongwoo Lee, Harmander Deogun, David Blaauw, and Dennis Sylvester

Interconnect Complexity-Aware FPGA Placement Using Rent's Rule. G. Parthasarathy, M. Marek-Sadowska, Arindam Mukherjee and Amit Singh

Matching-Based Algorithm for FPGA Channel Segmentation Design. Yao-Wen Chang, Jai-Ming Lin and M. D. F. Wong

Interconnect Resource-Aware Placement for Hierarchical FPGAs. Amit Singh, Ganapathy Parthasarathy, and Malgorzata Marek-Sadowska

Architectures and Algorithms for Synthesizable Embedded Programmable Logic Cores. Noha Kafafi, Kimberly Bozman, and Steven J.E. Wilton

Floorplanning of Pipelined Array Modules using Sequence Pairs. Matthew Moe and Herman Schmit

Maze Routing with Buffer Insertion and Wiresizing. Minghorng Lai and D.F. Wong

A Novel Net Weighting Algorithm for Timing-Driven Placement. Tim (Tianming) Kong

An Algorithm for Simultaneous Pin Assignment and Routing. Hua Xiang, Xiaoping Tang, and D.F. Wong

A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. Xiaoping Tang, Ruiqi Tian
, Hua Xiang, and D.F. Wong

Buffered Routing Tree Construction Under Buffer Placement Blockages. Wei Chen, Massoud Pedram, and Premal Buch

Ant Colony Optimization Technique for Macrocell Overlap Removal. Stelian Alupoaei and Srinivas Katkoori

Xtream-Fit: An Energy-Delay Efficient Data Memory Subsystem for Embedded Media Processing. Anand Ramachandran and Margarida F. Jacome

Exploiting Operation Level Parallelism through Dynamically Reconfigurable Datapaths. Zhining Huang and Sharad Malik

A Novel Combinational Testibility Analysis by Considering Signal Correlation. Shih-Chieh Chang, Shi-Sen Cheng, Wen-Bon Jone, and Chien-Chung Tsai

Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs. Amir H. Ajami, Kaustav Banerjee, Amit Mehrotra, and Massoud Pedram

Reducing Power Density through Activity Migration. Seongmoo Heo, Kenneth Barr, and Krste Asanovic

Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits. Yehea I. Ismail and Eby G. Friedman

Register-Transfer Level Estimation Techniques for Switching Activity and Power Consumption. Anand Raghunathan, Sujit Dey and Niraj K. Jha

On-Chip Inductance Cons and Pros. Yehea I. Ismail

Parameterized RTL Power Models for Soft Macros. Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, and Massimo Poncino