| Year |
|
Name |
Thesis |
Status |
|
2005 |
 |
陳勇志 |
An
Improved Approach for Alternative Wires Identification
(ICCD'05) |
Prof. at NTUST |
|
2005 |
 |
黃議樂 |
Language-Based
High Level Transaction Extraction on On-chip Buses
(ISQED'06) |
NVIDIA, US
|
|
2005 |
 |
蘇明宏 |
High
Level Equivalence Symmetric Inputs Identification
(ASPDAC'06) |
TSMC |
|
2005 |
 |
謝禎安 |
Probabilistic Approach for Logic Equivalence Checking
(ATS'06) |
|
|
2006 |
 |
莊旻倫 |
Reversible Sequential Element Designs
(ASPDAC'07)
(ACM JETC'08) |
Schneider Electric |
|
2006 |
 |
吳世傑 |
PEACH: A Novel Architecture for Probabilistic Combinational Equivalence
Checking
(ATS'06)
(VLSI -SoC'06)
(IEEE TVLSI'08) |
Synopsys |
|
2006 |
 |
李宗霖 |
Recognition of Fanout-free Functions
(ASPDAC'07) |
TPV |
|
2007 |
 |
邱創祺 |
A Statistic-based Approach to Testability Analysis
(ISQED'08) |
Google, TW |
|
2007 |
 |
蕭育霖 |
Multiple
Error Diagnosis in Large Combinational Circuits Using an Efficient
Parallel Vector Simulation
(VLSI-DAT'08) |
Synopsys |
|
2007 |
 |
蔡榮泰 |
Reachability
Analysis of Sequential Circuits (VLSI-DAT'10) |
Xilinx, US |
|
2007 |
 |
黃意元 |
A
Simulation-based Redundancy Identification in Combinational Circuits (VLSI Design/CAD'07) |
Foxconn |
| 2008 |
 |
林辰軒 |
Dependent Latch Identification in the Reachable State Space (ASPDAC'09
Best Paper Nominee)(IEEE
TCAD'09) |
Google, US |
| 2008 |
 |
張光榕 |
A
Cube-based Approach to Reachability Analysis
(VLSI-DAT'10) |
Synopsys, US |
| 2008 |
 |
劉怡伶 |
ACO-based Peak Power Estimation in VLSI Circuits (ISQED'09) |
Ph. D at Imperial College London, UK |
| 2008 |
 |
詹孟學 |
The
Testing Issues of System-in-Package Design Methodology (ISQED'09) |
Asus |
| 2008 |
 |
林俊吉 |
A
Universal Logic Restructuring Technique: IRredundancy Removal and
Addition (DATE'09) |
Meta, US |
| 2009 |
 |
張雅欣 |
GA2CO: Peak Temperature Estimation of VLSI Circuits (ISOCC'09) |
MediaTek |
| 2009 |
 |
林佳奇 |
Soft Error Rate Reduction by IRredundancy Removal and Addition |
Synopsys |
| 2009 |
 |
陳宏易 |
RTL Design Error Modeling and Verification |
|
| 2010 |
 |
李道明 |
Logic Restructuring Using Error Injection and Correction (ISOCC'12) |
MediaTek |
| 2010 |
 |
陳延安 |
An Efficient Register-Transfer Level Testability Estimation Technique Based on Monte Carlo Simulation (SOCC'11) |
TSMC |
|
2011 |
 |
林修毅 |
A Statically Probabilistic Analysis Method under Mutation Analysis for Functional Qualification (DATE'12)
|
TikTok, SG |
|
2011 |
 |
郭品宜 |
On Rewiring and Simplication for Canonicity in Threshold Logic Circuits (ICCAD'11) |
TSMC |
|
2011 |
 |
陳岱鈴 |
An Efficient Interpolation-based Projected Sum of Product Decomposition via Genetic Algorithm (JMVLSC) |
HTC |
|
2012 |
 |
唐立夫 |
An Efficient Enhanced Synthesis Algorithm for Reconfigurable Single-Electron Transistors Mapping (DATE'13) |
Asus |
|
2012 |
 |
楊晏琪 |
Genetic Algorithm-Based Pattern Generation for Mutation Analysis (ISCAS'13) |
NOVATEK |
|
2012 |
 |
江長恩 |
A Linear Threshold Gate-Based Approach Computing Product Terms for Reconfigurable Single-Electron Transistor Mapping (DATE'13) |
MediaTek |
|
2012 |
 |
蔡正寬 |
Static Timing Analysis for Threshold Logic Circuits (ICCAD'13) |
Silicon Motion |
|
2013 |
 |
林家君 |
On Minimizing the Implementation Cost of Threshold Network by Rewiring (DATE'14) |
TSMC |
|
2013 |
 |
陳瑞鴻 |
Making Combinational Circuits Cyclifiable (SOCC'15) |
MediaTek |
|
2013 |
 |
俞政杉 |
A Scalable Approach to Correctness Analysis and Optimization for Probabilistic Boolean Circuits (IEEE TCAD'15) |
MediaTek |
|
2013 |
 |
王治中 |
Enhancing Bounded Sequential Equivalence Checking Using Range-equivalent Circuits
(VLSI-DAT'18) (Best Paper Award) |
TSMC |
|
2014 |
 |
胡詠峻 |
Power Optimization for PBC (IEEE TCAD'15) |
Metaverse, UK |
|
2014 |
 |
翁婉禎 |
Using Structural Relations for Checking Combinationality of Cyclic Circuits (DATE'15) |
Synopsys |
|
2014 |
 |
紀韋安 |
Enhancing Bounded Sequential Equivalence Checking with Cross-Timeframe Optimization (VLSI-DAT'18) (Best Paper Award) |
MediaTek |
|
2014 |
 |
劉千瑋 |
Width Minimization in the Single-Electron Transistor Array Synthesis (DATE'14) (IEEE TVLSI'15) |
Synopsys |
|
2015 |
 |
鄒東臻 |
A Parabolic Hyperplane-based Approach to the Characterization of Ultra-low Voltage cell Library |
|
|
2015 |
 |
何清萱 |
Area-aware Decomposition for Single-Electron Transistor Arrays (ACM TODAES'16) |
Synopsys |
|
2015 |
 |
郭家堯 |
A Linear Programming Approach to Stochastic Circuits for Non-Linear Polynomial Functions |
Incentia |
|
2015 |
 |
周育民 |
MajorSat: A SAT Solver to Majority Logic (ASPDAC'16) |
MediaTek |
|
2015 |
 |
林振宇 |
Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks (IEEE TMSCS'16) |
RealTek |
|
2016 |
 |
李昀叡 |
Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays (IEEE TVLSI’17) |
Synopsys |
|
2016 |
 |
鍾郡哲 |
Minimization of Majority Logic Circuits Using Logic Implications (ASPDAC’17) |
Faraday |
|
2016 |
 |
黃喬緯 |
A Formal Approach to the Threshold Logic Network Optimization (ISQED’17) |
MediaTek |
|
2016 |
 |
陳亮元 |
The Testing Analysis of Cyclic Combinational Circuits and Its Application on SAT-Based Test Generation |
NVIDIA |
|
2017 |
 |
李東原 |
Logic Optimization with Considering Boolean Relations
(DATE'18) |
Cadence |
|
2017 |
 |
王馨珮 |
On Synthesizing Memristor-Based Logic Circuits with Minimal Operational Pulses(IEEE TVLSI'18) |
|
|
2017 |
 |
賴勇安 |
Synthesis of Approximate Threshold Logic Circuits with an Error Rate Guarantee
(DATE'18) |
Synopsys |
|
2018 |
 |
劉晉亨 |
Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments
(IEEE TCAD’19) |
MediaTek |
|
2018 |
 |
張晏萍 |
A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises
(SOCC’19) |
Synopsys |
|
2018 |
 |
王登甲 |
IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement
(ISQED'20) |
MediaTek |
|
2018 |
 |
吉德軒 |
A Glitch Key-Gate for Logic Encryption
(SOCC’19) |
AMD |
|
2019 |
 |
吳家承 |
Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model
(ACM JETC’21) |
MediaTek |
|
2019 |
 |
張雅鈞 |
A Convolutional Result Sharing Approach for Binarized Neural Network Inference
(DATE'20) |
MediaTek |
|
2019 |
 |
陳君瑞 |
Rehabilitation System for Limbs using IMUs
(ISQED'20) |
Asus |
|
2019 |
 |
李信璁 |
On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Array
(ISQED’21) |
Synopsys |
|
2019 |
 |
江孝友 |
LOOPLock : LOgic OPtimization based Cyclic Logic Locking
(IEEE TCAD'20) |
MediaTek |
|
2020 |
 |
楊翔閔 |
Security Analysis for a Cyclic Logic Locking Method - LOOPLock
(IEEE TCAD'22-1) |
TSMC |
|
2020 |
 |
林奕廷 |
An IMU-aided Fitness System
(SOCC'21) |
MediaTek |
|
2020 |
 |
柯昶丞 |
Majority Logic Circuit Minimization Using Node Addition and Removal
(IEEE TCAD'22-2) |
MediaTek |
|
2020 |
 |
黃宣豪 |
Cluster Tool Performance Analysis using Graph Database
(SOCC'21) |
MediaTek |
|
2020 |
 |
譚杰城 |
An Efficient Approximate Node Merging with an Error Rate Guarantee
(ASPDAC’21) |
MediaTek |
|
2020 |
 |
許文誌 |
On Reduction of Computation for Threshold Function Identification
(SOCC'21) |
Synopsys |
|
2021 |
 |
嚴心平 |
A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation
(ISQED'23) |
MediaTek |
|
2021 |
 |
魏聖修 |
A Flexible Result Sharing Approach Using Filter Repetitions to Binarized Neural Networks Optimization
|
RealTek |
|
2021 |
 |
陳姵珮 |
An Enhanced Cyclic Logic Locking Approach against SAT-based Attacks
(ICCAD'22)
(ASPDAC’24) |
Mentor Graphics |
|
2022 |
 |
林巧勳 |
Layout Hotspot Pattern Clustering Using a Density-based Approach
(VLSI-TSA'23) |
TSMC |
|
2022 |
 |
李俊廷 |
Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee
(ASPDAC’23) |
MediaTek |
|
2022 |
 |
蔡宥璿 |
Minimizing Computation in Binarized Neural Network Inference using Partial-Filter Sharing
(VLSI-TSA'23) |
MediaTek |
|
2022 |
 |
李孟憬 |
A Constructive Approach for Threshold Function Identification
(ACM TODAES'23)
(IEEE TCAD'24) |
MediaTek |
|
2022 |
 |
黃昱彰 |
Accelerating Binarized Neural Network Inference by Reusing Operation Results and Elevating Resource Utilization on Edge devices
(VLSI-TSA'23) |
Synopsys |
|
2022 |
 |
留孝倫 |
A Don't-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks
(IEEE TCAD’22-4)
(ASPDAC’23) |
Synopsys |
|
2023 |
 |
張永鋒 |
IR drop Prediction Based on Machine Learning and Pattern Reduction
(GLSVLSI'24)
|
MediaTek |
|
2023 |
 |
黃詮舜 |
An Efficient Approach to Iterative Network Pruning
(VLSI-TSA'24)
|
Synopsys |
|
2023 |
 |
李禹承 |
On Construction of Trajectory of Boxer’s Punch using a single IMU
|
NVIDIA |
|
2023 |
 |
唐梧遷 |
Model Reduction Using a Hybrid Approach of Genetic Algorithm and Rule-based Method
(SOCC’24)
|
Ph. D. at NTHU |
|
2023 |
 |
顏佑全 |
Threshold Logic Circuit Synthesis Using Dynamic Programming
(IEEE TCAD'24) |
Teacher Education at NTHU |
|
2024 |
 |
古庭羽 |
A Particle Swarm Optimization Approach to Approximate Logic Synthesis with an Error Rate Guarantee in Threshold Logic Networks
|
MediaTek |
|
2024 |
 |
鄭宇辰 |
Package Effects-aware Dynamic IR Drop Prediction with U-Net Model
|
MediaTek |
|
2024 |
 |
王承隆 |
A Retraining Technique for Model Reduction Using Knowledge Distillation
|
Mentor Graphics |
|
2024 |
 |
何雨澂 |
Observability-Aware Pattern Generation for Hardware Trojan Detection using Reinforcement Learning
|
Mentor Graphics |
|
2024 |
 |
周冠玲 |
A Genetic Algorithm-based Pruning for CNN Model Optimization
|
TSMC |
|
2024 |
 |
錢珈鋒 |
Improving CNN-based Pad Defect Classification with Enhanced Preprocessing Techniques
|
MicroIP |
|
2024 |
 |
林祐丞 |
A Mathematical Exploration to Equivalence Checking and Correction of Quantum Circuits
|
MicroIP |
|
2024 |
 |
許鎧博 |
IMU-based Motion Trajectory Reconstruction and Recognition with Dynamic Calibration on Embedded System Platform
|
NVIDIA |
|
2024 |
 |
李宇哲 |
Real-Time Dynamic IR-drop Prediction for IR ECO
|
Mentor Graphics |
