publications

Referred Journal Articles
31.	(IEEE TCAD) Yu-Chuan Yen, Meng-Jing Li, Yi-Ting Li, Yung-Chih Chen, Ihao Chen, and Chun-Yao Wang, "9-input Threshold Function Identification using a New Necessary Condition of Threshold Function", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2024. (to appear)
30.	(ACM TODAES) Meng-Jing Li, Yu-Chuan Yen, Yi-Ting Li, Yung-Chih Chen, and Chun-Yao Wang, "A Constructive Approach for Threshold Function Identification", ACM Transactions on Design Automation of Electronic Systems. pp. 86:1-86:19, vol. 28, No. 5, September, 2023.
29.	(IEEE TCAD) Hsiao-Lun Liu, Yi-Ting Li, Yung-Chih Chen, and Chun-Yao Wang, "A Don’t-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. pp. 4821-4825, vol. 41, No. 11, November, 2022.
28.	(IEEE TCAD) Chia-Chun Lin, Ciao-Syun Lin, You-Hsuen Tsai, Yung-Chih Chen, and Chun-Yao Wang, "Don’t Care Computation and De Morgan Transformation for Threshold Logic Network Optimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. pp. 1412-1422, vol. 41, No. 5, May, 2022.
27.	(IEEE TCAD) Chang-Cheng Ko, Chia-Chun Lin, Yung-Chih Chen, and Chun-Yao Wang, "Majority Logic Circuit Minimization Using Node Addition and Removal", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. pp. 642-655, vol. 41, No. 3, March, 2022.
26.	(IEEE TCAD) Xiang-Min Yang, Pei-Pei Chen, Hsiao-Yu Chiang, Chia-Chun Lin, Yung-Chih Chen, and Chun-Yao Wang, "LOOPLock 2.0 : An Enhanced Cyclic Logic Locking Approach", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. pp. 29-34, vol. 41, No. 1, January, 2022.
25.	(ACM JETC) Chia-Cheng Wu, Yi-Hsiang Hu, Chia-Chun Lin, Yung-Chih Chen, Juinn-Dar Huang, and Chun-Yao Wang, "Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model", ACM Journal on Emerging Technologies in Computing System. pp. 1-23, vol. 17, No. 2, January, 2021.
24.	(IEEE TCAD) Chia-Chun Lin, Chin-Heng Liu, Yung-Chih Chen, and Chun-Yao Wang, "A New Necessary Condition for Threshold Function Identification", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. pp. 5304-5308, vol. 39, No. 12, December, 2020.
23.	(IEEE TCAD) Hsiao-Yu Chiang, Yung-Chih Chen, De-Xuan Ji, Xiang-Min Yang, Chia-Chun Lin, and Chun-Yao Wang, "LOOPLock : LOgic OPtimization based Cyclic Logic Locking", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. pp. 2178-2191, vol. 39, No. 10, October, 2020.
22.	(IEEE TCAD) Chin-Heng Liu, Chia-Chun Lin, Yung-Chih Chen, Chia-Cheng Wu, Chun-Yao Wang, and Shigeru Yamashita, "Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. pp. 2284-2297, vol. 38, No. 12, December, 2019.
21.	(IEEE TVLSI) Hsin-Pei Wang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, and Chun-Yao Wang, "On Synthesizing Memristor-Based Logic Circuits with Minimal Operational Pulses", IEEE Transactions on Very Large Scale Integration Systems, pp. 2842-2852, vol. 26, No. 12, December, 2018.
20.	(IEEE TVLSI) Yun-Jui Li, Ching-Yi Huang, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, and Vijaykrishnan Narayanan, "Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays", IEEE Transactions on Very Large Scale Integration Systems, pp. 1477-1489, vol. 25, No.4, April, 2017.
19.	(IEEE TMSCS) Chen-Yu Lin, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, and Chiou-Ting Hsu, "Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks", IEEE Transactions on Multi-Scale Computing Systems, pp. 225-233, Vol. 2, No. 4, October-December, 2016.
18.	(ACM TODAES) Ching-Hsuan Ho, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Suma Datta, and Vijaykrishnan Narayanan, "Area-aware Decomposition for Single-Electron Transistor Arrays", ACM Transactions on Design Automation of Electronic Systems, Vol. 21, No. 4, Article 70, September 2016.
17.	(IEEE TVLSI) Ching-Yi Huang, Yun-Jui Li, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, and Vijaykrishnan Narayanan, "Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays", IEEE Transactions on Very Large Scale Integration Systems, pp. 2321-2334, June 2016.
16.	(JMVLSC) Tai-Lin Chen, Chun-Yao Wang, Ching-Yi Huang, and Yung-Chih Chen, "An Efficient Interpolation-based Projected Sum of Product Decomposition via Genetic Algorithm", Journal of Multiple-Valued Logic and Soft Computing, pp. 1-19, Vol. 27, No. 1, 2016.
15.	(IEEE TCAD) Ching-Yi Huang, Zheng-Shan Yu, Yung-Chun Hu, Tung-Chen Tsou, Chun-Yao Wang, Yung-Chih Chen, "Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 615-628, April 2015.
14.	(IEEE TVLSI) Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan, "Synthesis for Width Minimization in the Single-Electron Transistor Array", IEEE Transactions on Very Large Scale Integration Systems, pp. 2862-2875, December 2015.
13.	(IEEE TCAD) Yung-Chih Chen, Chun-Yao Wang, and Ching-Yi Huang, "Verification of Reconfigurable Binary Decision Diagram-based Single-Electron Transistor Arrays", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.1473-1483, October 2013.
12.	(ACM JETC) Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, and Vijaykrishnan Narayanan, "A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays", ACM Journal on Emerging Technologies in Computing System, Vol. 9, No. 1, Article 5, February 2013.
11.	(IEEE TCAD) Yung-Chih Chen, Chun-Yao Wang, "Logic Restructuring Using Node Addition and Removal", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.260-270, February 2012.
10.	(IEEE TCAD) Yung-Chih Chen, Chun-Yao Wang, "Fast Node Merging with Don’t Cares Using Logic Implications", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.1827-1832, November 2010.
9.	(IEEE TCAD) Chen-Hsuan Lin, Chun-Yao Wang, and Yung-Chih Chen, "Dependent Latch Identification in Reachable State Space", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.1113-1126, August 2009.
8.	(IEEE TCAD) Yung-Chih Chen, Chun-Yao Wang, "An Implicit Approach to Minimizing Range-Equivalent Circuits",, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.1942-1955, November 2008.
7.	(IEEE D&T) Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, and Jing-Yang Jou, "Verification on Pin-Accurate Port Connections", IEEE Design and Test of Computers, pp. 478-486, September/October. 2008.
6.	(IEEE TVLSI) Shih-Chieh Wu, Chun-Yao Wang, and Yung-Chih Chen, "Novel Probabilistic Combinational Equivalence Checking", IEEE Transactions on Very Large Scale Integration Systems, pp.365-375, April 2008.
5.	(ACM JETC) Min-Lun Chuang, Chun-Yao Wang, "Synthesis of Reversible Sequential Elements", ACM Journal on Emerging Technologies in Computing Systems, Vol. 3, No. 4, Article 19, January 2008.
4.	(IEEE TCAD) Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, and TingTing Hwang, "A Bus Encoding Scheme for Crosstalk Elimination in High Performance Processor Design", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.2222-2227, December 2007.
3.	(IEEE TCAD) Chun-Yao Wang, Shing-Wu Tung, and Jing-Yang Jou, "Automatic Interconnection Rectification for SoC Design Verification", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.104-114, January 2003.
2.	(IEEE TCAD) Chun-Yao Wang, Shing-Wu Tung, and Jing-Yang Jou, "An Automorphic Approach to Verification Pattern Generation for SoC Design Verification using Port Order Fault Model", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.1225-1232, October 2002.
1.	(IEEE TCAD) Chun-Yao Wang, Shing-Wu Tung, and Jing-Yang Jou, "On Automatic Verification Pattern Generation for SoC with Port Order Fault Model", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.466-479, April 2002.
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International Conferences
77.	(ISPACS'24) Yu-Cheng Lee, Kai-Po Hsu, Yun-Ju Lee, Yi-Ting Li, Wuqian Tang, Yung-Chih Chen, Wen-Hsin Chiu, and Chun-Yao Wang, "On Construction of Trajectory of Boxer’s Punch using a single IMU", 2024 IEEE International Symposium on Intelligent Signal Processing and Communication Systems. (to appear)
76.	(SOCC'24) Wuqian Tang, Chuan-Shun Huang, Yung-Chih Chen, Yi-Ting Li, Shih-Chieh Chang, and Chun-Yao Wang, "Model Reduction Using a Hybrid Approach of Genetic Algorithm and Rule-Based Method", 2024 IEEE International System-on-Chip Conference. (to appear)
75.	(GLSVLSI'24) Yong-Fong Chang, Yung-Chih Chen, Yu-Chen Cheng, Shu-Hong Lin, Che-Hsu Lin, Chun-Yuan Chen, Yu-Hsuan Chen, Yu-Che Lee, Jia-Wei Lin, Hsun-Wei Pao, Shih-Chieh Chang, Yi-Ting Li, and Chun-Yao Wang, "IR drop Prediction Based on Machine Learning and Pattern Reduction", 2024 ACM Great Lakes Symposium on VLSI, June 2024.
74.	(VLSI-TSA'24) Chuan-Shun Huang, Wuqian Tang, Yung-Chih Chen, Yi-Ting Li, Shih-Chieh Chang, and Chun-Yao Wang, "An Efficient Approach to Iterative Network Pruning", 2024 IEEE International VLSI Symposium on Technology, Systems and Applications, April 2024.
73.	(DATE'24) Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, and Chun-Yao Wang, "A Hybrid Approach to Reverse Engineering on Combinational Circuits", 2024 IEEE Design Automation and Test in Europe, March 2024.
72.	(ASPDAC'24) Pei-Pei Chen, Xiang-Min Yang, Yu-Cheng He, Yung-Chih Chen, Yi-Ting Li, and Chun-Yao Wang, "LOOPLock 3.0 : A Robust Cyclic Logic Locking Approach", 2024 IEEE Asia and South Pacific Design Automation Conference, January 2024.
71.	(ICCAD'23) Takashi Sato, Chun-Yao Wang, Yu-Guang Chen, and Tsung-Wei Huang, "Invited Paper: Overview of 2023 CAD Contest at ICCAD", 2023 IEEE International Conference on Computer-Aided Design, November 2023.
70.	(ISQED'23) Hsin-Ping Yen, Shiuan-Hau Huang, Yan-Hsiu Liu, Kuang-Hsien Tseng, Ji-Fu Kung, Yi-Ting Li, Yung-Chih Chen, and Chun-Yao Wang, "A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation", 2023 IEEE International Symposium on Quality Electronic Design, April 2023.
69.	(VLSI-TSA'23) Yu-Chang Huang, You-Hsuen Tsai, Yi-Ting Li, Yung-Chih Chen, and Chun-Yao Wang, "Accelerating Binarized Neural Network Inference by Reusing Operation Results and Elevating Resource Utilization on Edge devices", 2023 IEEE International VLSI Symposium on Technology, Systems and Applications, April 2023.
68.	(VLSI-TSA'23) You-Hsuen Tsai, Yu-Chang Huang, Yi-Ting Li, Yung-Chih Chen, and Chun-Yao Wang, "Minimizing Computation in Binarized Neural Network Inference using Partial-Filter Sharing", 2023 IEEE International VLSI Symposium on Technology, Systems and Applications, April 2023.
67.	(VLSI-TSA'23) Ciao-Syun Lin, Pin-Yian Tsai, Yan-Hsiu Liu, Yi-Ting Li, Yung-Chih Chen, and Chun-Yao Wang, "Layout Hotspot Pattern Clustering Using a Density-based Approach", 2023 IEEE International VLSI Symposium on Technology, Systems and Applications, April 2023.
66.	(ASPDAC'23) Chun-Ting Lee, Yi-Ting Li, Yung-Chih Chen, and Chun-Yao Wang, "Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee", 2023 IEEE Asia and South Pacific Design Automation Conference, January 2023.
65.	(ASPDAC'23) Hsiao-Lun Liu, Yi-Ting Li, Yung-Chih Chen, and Chun-Yao Wang, "A Robust Approach to Detecting Non-equivalent Quantum Circuits Using Specially Designed Stimuli", 2023 IEEE Asia and South Pacific Design Automation Conference, January 2023.
64.	(ICCAD'22) Pei-Pei Chen, Xiang-Min Yang, Yi-Ting Li, Yung-Chih Chen, and Chun-Yao Wang, "An Approach to Unlocking Cyclic Logic Locking - LOOPLock 2.0", 2022 IEEE International Conference on Computer-Aided Design, November 2022.
63.	(ICCAD'22) Yu-Guang Chen, Chun-Yao Wang, Tsung-Wei Huang, Takashi Sato, "Overview of 2022 CAD Contest at ICCAD", 2022 IEEE International Conference on Computer-Aided Design, November 2022.
62.	(ICCAD'21) Tsung-Wei Huang, Takashi Sato, Chun-Yao Wang, Yu-Guang Chen, "Overview of 2021 CAD Contest at ICCAD", 2021 IEEE International Conference on Computer-Aided Design, November 2021.
61.	(SOCC'21) Wen-Chih Hsu, Chia-Chun Lin, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang, "On Reduction of Computations for Threshold Function Identification", 2021 IEEE International System-on-Chip Conference, pp. 146-151, September 2021.
60.	(SOCC'21) Shiuan-Hau Huang, Hsin-Ping Yen, Yan-Hsiu Liu, Kuang-Hsien Tseng, Ji-Fu Kung, Chia-Chun Lin, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang, "Cluster Tool Performance Analysis Using Graph Database", 2021 IEEE International System-on-Chip Conference, pp. 230-235, September 2021.
59.	(SOCC'21) Yi-Ting Lin, Chun-Jui Chen, Pei-Yi Kuo, Si-Huei Lee, Chia-Chun Lin, Yun-Ju Lee, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang, "An IMU-Aided Fitness System", 2021 IEEE International System-on-Chip Conference, pp. 224-229, September 2021.
58.	(ISQED'21) Hsin-Tsung Lee, Chia-Chun Lin, Yung-Chih Chen, and Chun-Yao Wang, "On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays", 2021 IEEE International Symposium on Quality Electronic Design, April 2021.
57.	(ASPDAC'21) Chia-Chun Lin, Hsin-Ping Yen, Sheng-Hsiu Wei, Pei-Pei Chen, Yung-Chih Chen, and Chun-Yao Wang, "A General Equivalence Checking Framework for Multivalued Logic", 2021 IEEE Asia and South Pacific Design Automation Conference, pp. 61-66, January 2021.
56.	(ASPDAC'21) Kit Seng Tam, Chia-Chun Lin, Yung-Chih Chen, and Chun-Yao Wang, "An Efficient Approximate Node Merging with an Error Rate Guarantee", 2021 IEEE Asia and South Pacific Design Automation Conference, pp. 266-271, January 2021.
55.	(SOCC'20) Chia-Chun Lin, Kit Seng Tam, Chang-Cheng Ko, Hsin-Ping Yen, Sheng-Hsiu Wei, Yung-Chih Chen, and Chun-Yao Wang, "A Dynamic Expansion Order Algorithm for the SAT-based Minimization", 2020 IEEE International System-on-Chip Conference, pp. 271-276, September 2020.
54.	(ISQED'20) Chun-Jui Chen, Yi-Ting Lin, Chia-Chun Lin, Yung-Chih Chen, Yun-Ju Lee, and Chun-Yao Wang, "Rehabilitation System for Limbs using IMUs", 2020 IEEE International Symposium on Quality Electronic Design.
53.	(ISQED'20) Teng-Chia Wang, Yan-Ping Chang, Chun-Jui Chen, Yun-Ju Lee, Chia-Chun Lin, Yung-Chih Chen, and Chun-Yao Wang, "IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement", 2020 IEEE International Symposium on Quality Electronic Design.
52.	(DATE'20) Ya-Chun Chang, Chia-Chun Lin, Yi-Ting Lin, Yung-Chih Chen, and Chun-Yao Wang, "A Convolutional Result Sharing Approach for Binarized Neural Network Inference", 2020 IEEE Design Automation and Test in Europe, March 2020.
51.	(SOCC'19) Yan-Ping Chang, Teng-Chia Wang, Yun-Ju Lee, Chia-Chun Lin, Yung-Chih Chen, and Chun-Yao Wang, "A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises", 2019 IEEE International System-on-Chip Conference.
50.	(SOCC'19) De-Xuan Ji, Hsiao-Yu Chiang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, and Chun-Yao Wang, "A Glitch Key-Gate for Logic Locking", 2019 IEEE International System-on-Chip Conference.
49.	(ISVLSI'18) Chia-Cheng Wu, Kung-Han Ho, Juinn-Dar Huang, and Chun-Yao Wang, "Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays", IEEE Computer Society Annual Symposium on VLSI, pp 257-262, July 2018.
48.	(GLSVLSI'18) Chia-Cheng Wu, Tung-Yuan Lee, Yung-An Lai, Hsin-Pei Wang, De-Xuan Ji, Yan-Ping Chang, Teng-Chia Wang, Chin-Heng Liu, Chun-Yao Wang, and Yung-Chih Chen, " A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification", 2018 ACM Great Lakes Symposium on VLSI, pp 447-450, May 2018.
47.	(VLSI-DAT'18) Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin, and Chun-Yao Wang, " Using Range-equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking", 2018 IEEE International Symposium on VLSI Design, Automation and Test, April 2018. (Best Paper Award)
46.	(DATE'18) Yung-An Lai, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, and Chun-Yao Wang, " Efficient Synthesis of Approximate Threshold Logic Circuits with an Error Rate Guarantee", 2018 IEEE Design Automation and Test in Europe, March 2018.
45.	(DATE'18) Tung-Yuan Lee, Chia-Cheng Wu, Chia-Chun Lin, Yung-Chih Chen, and Chun-Yao Wang, " Logic Optimization with Considering Boolean Relations", 2018 IEEE Design Automation and Test in Europe, March 2018.
44.	(ISQED'17) Chia-Chun Lin, Chiao-Wei Huang, Chun-Yao Wang, and Yung-Chih Chen, " In&Out: Restructuring for Threshold Logic Network Optimization", 2017 IEEE International Symposium on Quality Electronic Design, pp. 413-418, March 2017.
43.	(ASPDAC'17) Chun-Che Chung, Yung-Chih Chen, Chun-Yao Wang, and Chia-Cheng Wu, " Majority Logic Circuits Optimisation by Node Merging", 2017 IEEE Asia and South Pacific Design Automation Conference, pp. 714-719, January 2017.
42.	(ASPDAC’16) Yu-Min Chou, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, " MajorSat: A SAT Solver to Majority Logic", 2016 IEEE Asia and South Pacific Design Automation Conference, pp. 480-485, January 2016.
41.	(ICCD’15) Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan, and Deming Chen, " CSL: Coordinated and Scalable Logic Synthesis Techniques for Effective NBTI Reduction", 2015 IEEE International Conference on Computer Design, pp. 257-264, October 2015.
40.	(SOCC’15) Jui-Hung Chen, Yung-Chih Chen, Wan-Chen Weng, Ching-Yi Huang, and Chun-Yao Wang, " Synthesis and Verification of Cyclic Combinational Circuits", 2015 IEEE International SOC Conference, pp. 257-262, September 2015.
39.	(DATE’15) Wan-Chen Weng, Yung-Chih Chen, Jui-Hung Chen, Ching-Yi Huang, Chun-Yao Wang, " Using Structural Relations for Checking Combinationality of Cyclic Circuits" , 2015 IEEE Design Automation and Test in Europe, pp. 325-328, March 2015. (Best Interactive Presentations Paper Nominee)
38.	(ASPDAC’15) Ching-Yi Huang, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, and Vijaykrishnan Narayanan, " A Defect-aware Approach for Mapping Reconfigurable Single-Electron Transistor Arrays" , 2015 IEEE Asia and South Pacific Design Automation Conference, pp. 118-123, January 2015.
37.	(ICCAD’14) Zheng Zhao, Chian-Wei Liu, Chun-Yao Wang and Weikang Qian, " BDD-Based Synthesis of Reconfigurable Single-Electron Transistor Array" , 2014 IEEE International Conference on Computer-Aided Design, pp. 47-54, November 2014.
36.	(DATE'14) Chia-Chun Lin, Chun-Yao Wang, Yung-Chih Chen, and Ching-Yi Huang, " Rewiring for Threshold Logic Circuit Minimization" , 2014 IEEE Design Automation and Test in Europe, March 2014.
35.	(DATE'14) Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, " Width Minimization in the Single-Electron Transistor Array Synthesis" , 2014 IEEE Design Automation and Test in Europe, March 2014.
34.	(ICCAD'13) Chen-Kuan Tsai, Chun-Yao Wang, Ching-Yi Huang and Yung-Chih Chen, " Sensitization Criterion for Threshold Logic Circuits and its Application" , 2013 IEEE International Conference on Computer-Aided Design, pp. 226-233, November 2013.
33.	(ISCAS'13) Yen-Chi Yang, Chun-Yao Wang, Ching-Yi Huang and Yung-Chih Chen, " Pattern Generation for Mutation Analysis Using Genetic Algorithms" , 2013 IEEE International Symposium on Circuits and Systems, pp. 2545-2548, May 2013.
32.	(DATE'13) Chang-En Chiang, Li-Fu Tang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen, Suman Datta and Vijaykrishnan Narayanan, " On Reconfigurable Single-Electron Transistor Arrays Synthesis Using Reordering Techniques" , 2013 IEEE Design Automation and Test in Europe, pp. 1807-1812, March 2013.
31.	(ISOCC'12) Ching-Yi Huang, Daw-Ming Lee, Chun-Chi Lin, and Chun-Yao Wang, " Error Injection & Correction: An Efficient Formal Logic Restructuring Algorithm" , 2012 IEEE International SoC Design Conference, pp. 188-191, November 2012.
30.	(DATE'12) Hsiu-Yi Lin, Chun-Yao Wang, Shih-Chieh Chang, Yung-Chih Chen, Hsuan-Ming Chou, Ching-Yi Huang, Yen-Chi Yang, and Chun-Chien Shen, " A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis", 2012 IEEE Design Automation and Test in Europe, pp. 147-152, March 2012.
29.	(ICCAD'11) Pin-Yi Kuo, Chun-Yao Wang, and Ching-Yi Huang, " On Rewiring and Simplification for Canonicity in Threshold Logic Circuits", 2011 IEEE International Conference on Computer-Aided Design, pp. 396-403, November 2011.
28.	(SOCC'11) Yen-An Chen, Chun-Yao Wang, Ching-Yi Huang, and Hsiu-Yi Lin, " A Register-Transfer Level Testability Analyzer", 2011 IEEE International SOC Conference, pp. 219-224, September 2011.
27.	(DAC'11) Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, and Vijaykrishnan Narayanan, "Automated Mapping for Reconfigurable Single-Electron Transistor Arrays", 2011 IEEE Design Automation Conference, pp. 878-883, June 2011.
26.	(DAC'10) Yung-Chih Chen, Chun-Yao Wang, "Node Addition and Removal in the Presence of Don’t Cares", 2010 IEEE Design Automation Conference, pp. 505-510, June 2010. (Best Paper Nominee)
25.	(VLSI-DAT'10) Jung-Tai Tsai, Chun-Yao Wang, and Kuang-Jung Chang, "Reachability Analysis of Sequential Circuits", 2010 IEEE International Symposium on VLSI Design, Automation and Test, pp. 181-184, April 2010.
24.	(ISOCC'09) Ya-Hsin Chang, Chun-Yao Wang, Yen-An Chen, "GA²CO: Peak Temperature Estimation of VLSI Circuits", 2009 IEEE International SoC Design Conference, pp. 345-348, November 2009.
23.	(ICCAD'09) Yung-Chih Chen, Chun-Yao Wang, "Fast Detection of Node Mergers using Logic Implications", 2009 IEEE International Conference on Computer-Aided Design, pp.785-788, November 2009.
22.	(GLSVLSI'09) Yung-Chih Chen, Chun-Yao Wang, "Enhancing SAT-based Sequential Depth Computation by Pruning Search Space", 2009 Great Lakes Symposium on VLSI, pp. 397-400, May 2009.
21.	(DATE'09) Chun-Chi Lin, Chun-Yao Wang, "Rewiring Using Irredundancy Removal and Addition", 2009 IEEE Design Automation and Test in Europe, pp.324-327, March 2009.
20.	(ISQED'09) Yi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, and Ya-Hsin Chang, "A Novel ACO-based Pattern Generation for Peak Power Estimation in VLSI Circuits", 2009 IEEE International Symposium on Quality Electronic Design, pp.317-323, March 2009.
19.	(ISQED'09) Meng-Syue Chan, Chun-Yao Wang, and Yung-Chih Chen, "An Efficient Approach to SiP Design Integration", 2009 IEEE International Symposium on Quality Electronic Design, pp.241-247, March 2009.
18.	(ASPDAC'09) Chen-Hsuan Lin, Chun-Yao Wang, "Dependent Latch Identification in the Reachable State Space", 2009 IEEE Asia and South Pacific Design Automation Conference, pp.630-635, January 2009. (Best Paper Nominee)
17.	(VLSI-DAT'08) Yu-Lin Hsiao, Chun-Yao Wang, and Yung-Chih Chen, "Multiple Error Diagnosis in Large Combinational Circuits Using an Efficient Parallel Vector Simulation", 2008 IEEE International Symposium on VLSI Design, Automation and Test, pp.109-112, April 2008.
16.	(ISQED'08) Chuang-Chi Chiou, Chun-Yao Wang, and Yung-Chih Chen, "A Statistic-based Approach to Testability Analysis", 2008 IEEE International Symposium on Quality Electronic Design, pp.267-270, March 2008.
15.	(ISQED'07) Yu-Min Kuo, Cheng-Hung Lin, Chun-Yao Wang, Shih-Chieh Chang, and Pei-Hsin Ho, "Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure", 2007 IEEE International Symposium on Quality Electronic Design, pp.344-349, March 2007.
14.	(ASPDAC'07) Min-Lun Chuang, Chun-Yao Wang, "Synthesis of Reversible Sequential Elements", 2007 IEEE Asia and South Pacific Design Automation Conference, pp.420-425, January 2007.
13.	(ASPDAC'07) Tsung-Lin Lee, Chun-Yao Wang, "Recognition of Fanout-free Functions", 2007 IEEE Asia and South Pacific Design Automation Conference, pp.426-431, January 2007.
12.	(ATS'06) Shih-Chieh Wu, Chun-Yao Wang and Jan-An Hsieh, "The Potential and Limitation of Probability-Based Combinational Equivalence Checking", 2006 IEEE Asian Test Symposium, pp.103-108, November 2006.
11.	(VLSI-SoC'06) Shih-Chieh Wu, Chun-Yao Wang, "PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking", IFIP/IEEE International Conference on Very Large Scale Integration, pp.104-109, October 2006.
10.	(ISQED'06) Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, and Yung-Chih Chen, "Language-Based High Level Transaction Extraction on On-chip Buses", 2006 IEEE International Symposium on Quality Electronic Design, pp.231-236, March 2006.
9.	(ASPDAC'06) Ming-Hong Su, Chun-Yao Wang, "High Level Equivalence Symmetric Input Identification", 2006 IEEE Asia and South Pacific Design Automation Conference, pp.249-253, January 2006.
8.	(ICCD'05) Yung-Chih Chen, Chun-Yao Wang, "An Improved Approach for Alternative Wire Identification", 2005 IEEE International Conference on Computer Design, pp.711-716, October 2005.
7.	(ITC'04) Geeng-Wei Lee, Chun-Yao Wang, Juinn-Dar Huang, and Jing-Yang Jou, "Verification on Port Connections", 2004 IEEE International Test Conference, pp.830-836, October 2004.
6.	(ICCD'04) Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, and Jing-Yang Jou, "Graph automorphism-based algorithm for determining symmetric inputs", 2004 IEEE International Conference on Computer Design, pp.417-419, October 2004.
5.	(ISCAS'03) Chun-Yao Wang, Shing-Wu Tung, and Jing-Yang Jou, "SOC Design Integration by Using Automatic Interconnection Rectification", 2003 IEEE International Symposium on Circuits and Systems, pp.744-747, May 2003.
4.	(ASPDAC'03) Chun-Yao Wang, Shing-Wu Tung and Jing-Yang Jou, "An Automatic Interconnection Rectification Technique for SoC Design Integration", 2003 IEEE Asia and South Pacific Design Automation Conference, pp.104-114, January 2003.
3.	(HLDVT'01) Chun-Yao Wang, Shing-Wu Tung, and Jing-Yang Jou, "On Generation of The Minimum Pattern Set for Data Path Elements in SoC Design Verification Based on Port Order Fault Model", 2001 IEEE International High-Level Design Validation and Test Workshop, pp.145-150, November 2001.
2.	(ATS'01) Chun-Yao Wang, Shing-Wu Tung, and Jing-Yang Jou, "An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model", 2001 IEEE Asian Test Symposium, pp.431-436, November 2001.
1.	(ISCAS'01) Chun-Yao Wang, Shing-Wu Tung, and Jing-Yang Jou, "An AVPG for SoC Design Verification with Port Order Fault Model", 2001 IEEE International Symposium on Circuits and Systems, pp.259-262, May 2001.
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Domestic Conferences
8.	Yung-Chih Chen, Chun-Yao Wang, "Enhancing SAT-based Sequential Depth Computation by Pruning Search Space", the 20^th VLSI Design/CAD Symposium, August 2009.
7.	Yi-Ling Liu, Chun-Yao Wang, "ACO-based Peak Power Estimation in VLSI Circuits", the 19^th VLSI Design/CAD Symposium, August 2008.
6.	Yi-Yuan Huang, Chun-Yao Wang, "A Simulation-based Redundancy Identification in Combinational Circuits", *the 18^th* VLSI Design/CAD Symposium, August 2007.
5.	Min-Lun Chuang, Chun-Yao Wang, "Reversible Sequential Element Designs", *the 17^th* VLSI Design/CAD Symposium, August 2006.
4.	Ming-Hong Su, Chun-Yao Wang, "High Level Equivalence Symmetric Input Identification", the 16^th* VLSI Design/CAD Symposium,* August 2005.
3.	Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, and Jing-Yang Jou, "On Automatic Verification Pattern Generation for SoC with Automorphism Technique", *the 15^th* VLSI Design/CAD Symposium, August 2004.
2.	Chun-Yao Wang, Shing-Wu Tung and Jing-Yang Jou, "On Generation of the Minimum Pattern Set for Data Path Elements in SoC Design Verification Based on Port Order Fault", the 12^th VLSI Design/CAD Symposium, August 2001.
1.	Chun-Yao Wang, Shing-Wu Tung and Jing-Yang Jou, "Searching Space Reduction of Port Order Fault ATPG", the 10^th VLSI Design/CAD Symposium, August 1999.